Semiconductor device with improved connection to control electrode region

ABSTRACT

In a semiconductor device with a control grid and comprising at least three semiconductor layers of alternately different conductivity types, portions of the second layer are protruded through the first layer to be exposed on the surface of the first layer, second electrode is mounted on the exposed portions in ohmic contact therewith, a third electrode is mounted to insulating cover the second electrode and the exposed portions containing the same, and the third electrode is in ohmic contact with the first layer.

United States Patent Inventor Michio Otsuka Yokohama, Japan Appl. No.80,110.

Filed Oct. 12, 1970 Patented Nov. 9, 1971 Assignee Tokyo ShibauraElectric Co., Ltd. Kawasaki-shi, Japan Priorities Oct. 13, 1969 Japan44/81156; Nov. 7, 1969, Japan, No. 44/88695; Nov. 22, 1969, Japan, No.44/933154 SEMICONDUCTOR DEVICE WITH IMPROVED CONNECTION TO CONTROLELECTRODE REGION 8 Claims, 25 Drawing Figs.

US. Cl 317/235, 317/234, 29/576 Int. Cl H011 5/02 Field of Search317/234, 235, 237-241 [56] References Cited UNITED STATES PATENTS3,474,303 10/1969 Lutz 317/234 3,475,235 10/1969 Nawalk et a1. 148/1903,476,992 11/1969 Chu 317/235 3,480,802 11/1969 Longini 317/235 XPrimary Examiner-James D. Kallam Attorney-Flynn & Frishauf PATENTEDunv9|97| sum 1 or 9 F l 6. 1A

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SEMICONDUCTOR DEVICE WITH IMPROVED CONNECTION TO CONTROL ELECTRODEREGION This invention relates to semiconductor device more particularlyto improved connection to the control electrode of a semiconductordevice with a control electrode or gate electrode.

In a semiconductor device having a control electrode, such as atransistor or a semiconductor-controlled rectifier element (for examplethyristor) the lateral resistance of the semiconductor substrateincreases with the surface area thereof so that the control effect ofthe control electrode upon the emitter region or cathode regiondecreases with the distance from the control electrode. Especially, inthe case of a power semiconductor device, as the area of the emitterregion or cathode region (hereinafter both regions are designated merelyas the emitter region) this problem becomes serious. For this reason, asis well known in the art, for the power semiconductor-controlledrectifier element the control electrode is formed in the shape of anannulus or a comb whereas in the case of the transistor, a modified combshape or an overlay construction is used, thus improving the arrangementof the control electrode region with respect to the cathode region forthe purpose of eliminating the above-described defect. With these priorconstructions, however, the relative arrangement between the controlelectrode (that is the base electrode, in the case of a transistorwhereas the gate electrode, in the case of a thyristor) and the emitterelectrode (that is the cathode electrode, in the case of the thyristor)is extremely complicated. On the other hand, since the effective valueof the main or output current of a semiconductor element with a controlelectrode is related to the area of the emitter electrode, in the powersemiconductor element, it is essential to make as large as possible thearea of the emitter electrode. Nevertheless, in the prior artsemiconductor devices, as the construction of the leads of the emitterelectrode and control electrode has been extremely complicated it hasbeen impossible to increase the area of the control electrode thusrendering difficult to manufacture high-power semiconductor elements.When the area of the gate electrode of a semiconductor-controlledrectifier element is increased, the gate current required to ignite itincreases. This problem is also required to be solved. In addition, itis also desired to increase the rate of rise of forward current di/dt byconcurrently igniting the entire cathode region.

It is the principal object of this invention to provide a new andimproved semiconductor device wherein the relative arrangement of thecontrol electrode and emitter electrode is greatly simplified.

A further object of this invention is to provide a grid-controlledsemiconductor device wherein the control electrode can effectivelycontrol the entire emitter region with simplified relative arrangementof the control electrode and emitter electrode.

Still further object of the invention is to provide a grid-controlledsemiconductor element or rectifier element with simplified relativearrangement of the control electrode and emitter electrode wherein therate of rise of the anode current is increased.

The semiconductor device comprises at least first, second and thirdsemiconductor layers of alternate conductivity type; a first electrodeelectrically connected to the last layer; the first layer including atleast one main region having an area in which portions of the secondlayer are exposed at the surface level of the first layer; by protrudingthrough the first layer; a second electrode in ohmic contact with theexposed portions of the second layer; and a third electrode overlyingthe main region of the first layer and insulated from the underlyingsecond electrode and from the exposed portions of the second layer; thethird electrode being in ohmic contact withthe main region in the firstlayer so as to cover the second electrode and the exposed portions ofthe second layer.

The second electrode constitutes a control electrode and the thirdelectrode an emitter electrode. According to this invention, as theemitter electrode is disposed to overly and insulated from the controlelectrode, these electrodes can be arranged neatly. This arrangementmakes it possible to dispose the first semiconductor layer constitutingthe emitter layer and the second semiconductor layer constituting thecontrol electrode layer in intricated configurations in substantiallythe same plane. Proper intrication of the emitter region and the controlelectrode region assures efficient control effect of the controlelectrode throughout the entire emitter region. This electrodearrangement further increases the areas of the emitter region and of thecontrol electrode region. Thus, this invention can remove priorlimitations of the construction of power semiconductor devices.

In this manner, in accordance with this invention, it is possible toprovide a transistor having a substrate comprising three semiconductorlayers with improved relative arrangement of emitter electrode and thebase electrode and to provide a semiconductor-controlled rectifierelement having a substrate comprising four semiconductor layers withimproved relative arrangement of the gate electrode and the cathodeelectrode.

According to another feature of this invention there is provided asemiconductor-controlled rectifier element of improved rising rate ofthe anode current by adding an auxiliary region to the first layer andby properly arranging the auxiliary region, a fourth electrode attachedto the second electrode and the main region.

The invention can be more fully understood from the following detaileddescription taken in conjunction with the accompanying drawings whichare depicted with some portions exaggerated. In the Drawings:

FIG. 1A shows a plan view of a thyristor embodying this invention;

FIG. 1B is a sectional view taken along a line IB-IB-in FIG. 1A;

FIG. 1C is an enlarged view of a portion of FIG. 18;

FIG. 2A shows a plan view of a modified thyristor;

FIG. 2B shows a sectional view taken along a line IlB-IIB in FIG. 2A;

FIGS. 3 and 4 show plan views of other modified thyristors;

FIG. 5A shows a plan view of a transistor embodying this invention;

FIG. 5B is a sectional view taken along a line VB-VB in FIG. 5A;

FIG. 6A shows a plan view of a thyristor wherein the first layer of thesemiconductor substrate comprises a main region and an auxiliary regionseparated from the main region;

FIG. 6B shows a section of the thyristor shown in FIG. 6A taken along aline VIB-VIB;

FIG. 6C shows a section taken along a line VIC-VIC in FIG. 6A;

FIG. 7A shows a plan view of a modification of the thyristor shown inFIG. 6;

FIG. 7B shows a sectional view of the thyristor shown in FIG. 7A takenalong a line VIIB-VIIB;

FIG. 8 is a plan view of another modified thyristor;

FIG. 9 is a plan view of still another modified thyristor;

FIG. 10A is a plan view of further modified thyristor;

FIG. 108 shows a section thereof taken along a line XB- X8 in FIG. 10A;

FIG. 11A shows a plan view of still another form of a thyristorembodying the invention;

FIG. 11B shows a sectional view taken along a line XIB- XIB in FIG. lIA;

FIG. 12A shows a modified thyristor in which the first layer of thesemiconductor substrate comprises an main region and an auxiliary regioncontiguous with the main region;

FIG. 128 shows a section of the thyristor shown in FIG. [2A taken alonga line XIIBXIIB;

FIG. 13 is a plan view of a modification of the thyristor shown in FIGS.12A and 123;

FIG. 14 shows a plan view of a modification of the thyristor shown inFIGS. 12A and 12B; and

FIG. 15 is a plan view of a yet another modification of the thyristorshown in FIGS. 12A and 12B.

FIGS. 1A and i3 show a construction of a thyristor having asemiconductor substrate 1 comprising four layers, viz a first layer N,,as second layer P,, a third layer N and a fourth layer P which havealternately different conductivity types and are laminated one upon theother. A first, or anode electrode 3 is connected to the fourth layer Pthrough an aluminum layer 2. The first layer N, includes a main regionhaving several areas through which portions of the second layer P, areexposed at the surface of the first layer N,. To these exposed portions4 is secured a plurality of second or gate electrodes 5 to provide ohmiccontacts. As shown in FIG. 1A, a respective ends of the gate electrodes5 are connected in common to a main gate electrode 6. A third or cathodeelectrode 7 is provided in ohmic contact with the first layer N, tooverlie respective gate electrodes and exposed portions 4 of the secondlayer. An insulator film 8 of SiO,, SiO or low-melting glass is appliedon two adjacent exposed portions 4 and the gate electrode 5therebetween, whereby these portions 4 and the gate electrode 5 areelectrically insulated from the cathode electrode 7. Thus, the gateelectrodes 5 are evenly distributed throughout the first layer N, andthe cathode region in the ducts formed in the cathode electrode 7 andinsulated therefrom.

The semiconductor device of the above construction can be fabricated inthe following manner, for example. First, an N- type semiconductorsubstrate is prepared and a trivalent metal, Ga, for instance, isdiffused into the opposite surfaces of the substrate as the impurity toprepare a semiconductor substrate having three layers P,, N and P Thenby means of the well-known selective diffusion technique the first layeror N, layer is formed in the layer P, as shown in FIG. 1B. In theexposed portions 4 between spaced apart portions of layer N, are formedP regions 9 by the well-known diffusion technique for facilitating theohmic connection to the gate electrodes 5 which are formed on the Pregions by applying suitable metal by vacuum vapor deposition orelectroplating. After application of the insulator layers 8 on theexposed portions 4 of layer N, and the gate electrodes 5 containedtherein a metal such as aluminum or gold is vapor deposited to form thecathode electrode 7. An anode electrode 3 of tungsten or molybdenum issecured to the semiconductor layer P by alloying method via a thin layerof aluminum 2. The anode electrode 3 also serves as a temperaturecompensating plate.

In the semiconductor device described above, control voltage isimpressed across the gate electrodes 5 and the cathode electrode 7 tocontrol the current (anode current) flowing between the cathode andanode electrodes. As above described, according to this invention, sincethe gate electrodes 5 are uniformly distributed throughout the entiresurface of the cathode region (layer N,) it is possible to uniformlyapply for forward bias voltage over the entire area of the cathoderegion, thus enabling simultaneous ignition of the thyristor over theentire area of the cathode region. This greatly improves the risingrate, that is the di/dt characteristics of the anode current and togreatly reduce the turn on time of the thyristor. Thus, it will be notedthat, according to this invention, it is quite easy to distribute gateelectrodes 5 in the cathode region 7 in an intricated configuration.

It will also be clear that the invention can be worked out in a numberof forms as described in the following. In the following modificationsthe same or corresponding portions are designated by the same referencenumerals for the sake of description.

In the modified thyristor shown in FIGS. 2A and 2B, gate electrodes 5are arranged radially and the common gate electrode 6 in the form of anannulus. This arrangement of the gate electrodes is suitable for the GTOSCR (gate turn off silicon controlled rectifier) whose anode current canbe turned off by applying a control potential upon the gate electrodes.A circular disc shaped cathode electrode 7 is provided to cover radiallydisposed gate electrodes 5, and the radially disposed portions 4 of thelayer P, and the gate electrodes 5 contained therein are insulated fromthe cathode electrode 7 by insulating layers 8 and the exposed portions4 are covered by the cathode electrode. Layers P,, N and P, are formedin the same manner as in the previous embodiment. After forming the gateelectrodes 5 in the prescribed portions of the second layer P, theexposed portions of the layer P, and the gate electrodes formed thereinare covered by insulator layers 8 of SiO, SiO or low-melting glass andthen a metal film of Au-Sb alloy, for example, is alloyed to the layerP, thus forming the cathode electrode 7 and the emitter region (cathoderegion) at the same time. When the cathode electrode 7 and the commonannular gate electrode 6 are interconnected through a high'resistanceresistor Rg of several hundred ohms to several kilohms, as shown in FIG.2B, sufficiently high short circuited emitter effect can be manifested.

In the embodiment shown in FIG. 3 exposed portions 4 of the second layerP, and the gate electrodes 5 formed on these portions are parallel witheach other and the common gate electrode 6 is positioned on one side ofthe gate electrodesv This type of thyristor is called side-gate-typethyristor. The sectional configuration is similar to that of the firstembodiment. In the fourth embodiment of this invention shown in FIG. 4,a plurality of exposed portions of the layer P, are formed along aplurality of concentric circles, and a corresponding number of arcuategate electrodes 5 contained in respective exposed portions are connectedto a common gate electrode 6 located at the center of the concentriccircles. This type of thyristor is termed as the center gate typethyristor.

In the fifth embodiment of this invention shown in FIGS. SA and 5B, thesemiconductor substrate la comprises three layers N,, P, and N and afirst electrode or a collector electrode 3a is joined to the lower sideof the third layer N,. The first layer N, or the emitter region isformed by any well-known technique such that exposed portions of thesecond layer P, or the base region are distributed on the surface of thefirst layer N, with a desired pattern. Portions of the base region towhich electrodes are to be mounted are converted into P regions as hasbeen described in connection with the first embodiment and baseelectrodes 5a are formed on these P regions. The surfaces of the exposedportions 4 and the base electrodes contained therein are covered byinsulating layers 8 of SiO,, for example. A third electrode, or anemitter electrode 7a is provided to cover electrode 50, in ohmic contactwith the first layer N As shown in FIG. 5A, the base electrodes 50 takea form of a matrix or lattice and are electrically connected to a commonbase electrode 6a. This modified element can be fabricated by a methodsimilar to that of the first embodiment excepting the emitter and baseelectrodes. The semiconductor element of this embodiment is sealed in anenvelope and connected to exterior electrodes by means of solder orslidable contacts such as spring means or the like.

As has been pointed out hereinabove, in conventional thyristors,increased area of the second layer of P, layer or the control regionrequires larger control current. it is also desired to increase thedi/dt characteristic. rnain According to this invention, the first layeris divided into a main region and an auxiliary region, the gateelectrodes provided in the portions of the second layer exposed in themain region are electrically connected to the auxiliary region. A maingate electrode is formed on the second layer such that the auxiliaryregion is positioned between the main gate electrode and the main regionwhereby to provide a thyristor manifesting improved di/dt characteristicwith small control current.

FIGS. 6A and 6B illustrate the construction of a thyristor of this type.The semiconductor substrate 1 of this thyristor is comprised by fourlaminated layers N,, P,, N, and P in the same manner as in the firstembodiment. However, as shown in FIG. 6A the first layer comprises amain region N, and an auxiliary region N, which are separated from eachother. The first to fourth layers are formed in the same manner as inthe first embodiment. Further, as shown in FIGS. 6A to 6C, therelationship among the gate electrodes 5, insulators 8, cathodeelectrode 7, regions P,, regions N, and the common electrode 6 in themain region is the same as in the first embodiment.

However, a main gate electrode is formed on the exposed portion of thesecond layer P, adjacent the auxiliary region N by ultrasonic-weldingtechnique, for example. The auxiliary region N is positioned between themain region N, and the main electrode 10 as shown in FIGS. 6A and 6C.Respective gate electrodes 5 are electrically connected to the auxiliaryregion N,.

In operation, the thyristor of this embodiment is biased forwardly. Inother words, a voltage is applied such that the anode electrode isbiased positively and the cathode electrode negatively. Further, asource of control voltage is connected between the main gate electrode10 and the cathode electrode 7 such that the main gate electrode 10 isbiased positively. Then the gate current flows through a passage whichcan be traced through main gate electrode 10, region P,, region N gateelectrodes 5, region P, region P,, region N and main region N, occursimultaneously. However, as the density of electrons injected from theauxiliary region N is much higher than that of the electrons from themain region N,, at first, portions of four layers N P,, N, and Pconfronting the auxiliary region N are ignited. This ignition currentflows through a passage through the gate electrodes 5, P region, P,regions, cathode region N, and cathode 7 so that the entire main regionN, (cathode region) is uniformly and strongly biased forwardly, with theresult that substantially the entire surface of the first layer (cathoderegion) is uniformly ignited. For this reason it is possible to decreasethe gate current. Even with such a small gate current it is possible togreatly decrease the rising period of the anode current (the currentflowing through electrodes 3 and 7), thus greatly improving the di/dtcharacteristics of the thyristor. When the thyristor are manufacturedwith their resistances between gate electrodes 5 and the main cathoderegion (layer N,) equal to several ohms to several hundred ohms it ispossible to maximize the di/dt characteristic, for example from 800A./p.s to 1000 A./p.s.

With this construction, since gate electrodes 5 are distributed in anarea beneath the cathode electrode 7, when the cathode region and gateregions are interconnected through a resistor having a resistance valueof several hundreds to several kilohms, sufficiently high shortcircuited emitter effect can be provided.

FIGS. 7A and 7B show a modification of the thyristor shown in FIGS. 6Ato 6C. In this embodiment gate electrodes 5 are formed in the axialdirection and a common annular gate electrode 6 connected to the outerends of the gate electrode is electrically connected to an annularauxiliary region N through an annular electrode 6b. Gate electrodes 5formed in the exposed portions of the layer P, in the main region aswell as these exposed portions are electrically insulated from overlyingcathode electrode 7. Regions N, and N; are formed by alloying ordiffusion process. More particularly, the N, region and cathodeelectrode 7 are formed simultaneously by a method comprising the stepsof forming gate electrodes 5 on the prescribed portions of layer P,,applying insulator films of SiO, SiO low-melting glass on the exposedportions of the layer P, and gate electrodes 5 contained therein, andthen alloying a foil of Au-Sb, for example, on the predetermined area ofthe layer P,. The thyristor of this embodiment functions with the sameadvantages as the embodiment shown in FIGS. 6A to 6C.

FIG. 8 shows a modified embodiment of the thyristor shown in FIGS. 6A to6C. This modification is of the side-gate type wherein a main gateelectrode 10 and an auxiliary region N;, are formed at a portion nearthe periphery of the substrate 1. The relative arrangement between thegate electrodes 5 and the cathode electrode 7, when viewed in asectional view, is similar to that of the embodiment shown in FIGS. 6Ato 6C except that a common gate electrode 6 for respective parallel gateelectrodes 5 intersects at right angles the central portions thereof.

FIG. 9 shows a further modification of the side-gate-type thyristorshown in FIG. 8. This embodiment is different from that shown in FIG. 8only in that the gate electrodes 5 intersect the common gate electrode 6in the form of symmetrical branches of a tree and that a main gateelectrode 10 of a small area is formed onthe layer P,.

FIGS. 10A and 10B show a center-gate-type thyristor. In this embodiment,the main region N, is in the form of a circular annulus and anindependent auxiliary region N is disposed at the center of the mainregion N,. A main gate electrode 10 is formed on the region P, at thecenter of the auxiliary region N Like the embodiment shown in FIG. 7,gate electrodes 5 are disposed radially and their annular common gateelectrode 6 is disposed at the center of a circular disc-shapedsubstrate 1. This embodiment is characterized in that it is easy tointerconnect the main gate electrode 10 and the cathode electrode 7through a resistor of a value of several hundred ohms to several kilohmsthus obtaining the desired short circuited emitter effect.

FIGS. 11A and 118 show still further modification of the thyristor shownin FIGS. 6A to 6C. It differs from that shown in FIGS. 6A to 6C in thatthe cathode electrode comprises two unitary portions 7 and 7b and thatthe'exposed portions 4 of the layer P, and gate electrode 5 contained inthese exposed portions are insulated from the cathode electrode byairgaps 80. More in detail, gate electrodes 5 are formed on the exposedportions 4 of the layer P, and portions 7 of the cathode of Au, Al orthe like are formed on the N, region. The height of portions 7 is madelarger than that of the gate electrodes 5 and a combinedtemperature-compensating plate and cathode plate 7b of tungsten ormolybdenum is slidably urged against cathode electrode portions 7 orsoldered thereto. When so constructed, the exposed portions 4 of layerP, and gate electrodes 5 contained therein are insulated from thecathode structure by airgaps 8a.

While in the embodiment shown in FIGS. 6A to 6C a construction of athyristor was shown wherein the first layer was divided into separatedmain and auxiliary regions so as to improve the di/dt characteristicwith smaller control current, the same advantage as well as sufficientlylarge short circuited emitter effect can also be provided by merelydividing the first layer into contiguous main and auxiliary zones.

One example of such a construction of the thyristor is illus trated inFIGS. 12A and 128. In the construction shown in FIGS. 12A and 12B, thesemiconductor substrate 1 including the second to fourth layers P,, N,and P gate electrodes 5, and cathode electrode 7 are fabricated in thesame manner as in the embodiment shown in FIGS. 6A to 6C.

As shown in FIG. 12B, portions of the first layer N, to the left of adash and dot line 11 constitute the main region b whereas portions tothe right constitute the auxiliary region a. The gate electrodes 5 areformed on the exposed portions of the layer P, in the main region bwhereas an electrode 6 common to these gate electrodes 5 is electricallyconnected onto the surface of the layer N in the auxiliary region a. Inother words, the gate electrodes 5 are in the form of stripes on acommon plane, as shown in FIG. 12A. The thickness of the layer N, atportions between main and auxiliary regions b and a and including thedot and dash line is thinner than that of the other portion. In the mainregion b, the exposed portions of layer P, and the gate electrodes 5contained therein are covered by insulator layers 8 and the cathodeelectrode 7 is in ohmic contact with the layer N, in the main region bthus covering exposed portions and gate electrodes. The main gateelectrode 10 is secured to the layer P, at a portion close to one sideof layer N,. A combined heat-compensating plate and anode electrode 3made of tungsten or molybdenum is alloyed to the bottom of layer Pthrough a foil of aluminum or the like 2. In some case, it isadvantageous to decrease the thickness of layer N, so that portionsthereof underlying the cathode electrode 7 may have suitable resistancevalue, for example from several ohms to several kilohms.

In operation, a forward bias is applied across anode electrode 3 andcathode electrode 7, making the former positive and the latter negative,and a source of control potential is connected between the main gateelectrode 10 and the cathode electrode 7, biasing positively the maingate electrode 10 with respect to the cathode electrode 7. Then, thegate current will flow from the main gate electrode 13 to the cathodeelectrode 7 through region P and region N 1 divided by dot and dash line11. Consequently, carriers are firstly injected into confrontingportions of four layers N,, P,, N and P of the auxiliary region a, thusigniting these portions. A. portion of the ignition current flows intothe cathode electrode 7 directly through the portion of the layer Nclose to the ignited portions and the remaining portions of the ignitioncurrent flow from gate electrodes 5 in the form of stripes to thecathode electrode 7 via P, region, and N or the main region, thusforwardly biasing the entire cathode regions confronting the main regionb. Thus, immediately after ignition of the four layer portions of theauxiliary region a, the four layer portions of the main region b areignited. When the resistance of the layer N between the common gateelectrode 6 and the cathode electrode 7 is selected to a suitable valueit is possible to minimize the time interval or time delay betweenignitions of the auxiliary region a and of the main region 12. Thisdecreases the buildup time of the main anode current and hence improvingthe di/dr characteristic of the thyristor even with small gate current.When the resistance value of the layer N between the gate electrodes 5and cathode electrode 7 is controlled from several ohms to severalhundred kilohms it is possible to manufacture thyristors having improveddi/dt characteristics of from 800 A./,u.s to 1000 A./p.s.

This embodiment is characterized in that layers P and N in the mainregion I) are short circuited by the resistance in the layer N bridgingthe auxiliary region a and the main region b thus providing sufficientlyhigh short circuited emitter effect without employing any additionalresistor.

FIG. 13 shows a modification of the thyristor shown in FIGS. 12A and128. This embodiment is different from that shown in FIGS. 12A and 1213in that the gate electrodes 5 are arranged in the radial direction withtheir outer ends connected to the annular common gate electrode 6. Thearea underlying the cathode electrode 7 serves as the main region andthe relationship between the gate electrodes 5 and the cathode electrode7 is the same as that of the former embodiment, when viewed in asectional view. Layer N shown close to the main gate electrode 10represents the auxiliary region.

FIG. 14 shows a plan view of a further modification of the embodimentshown in FIGS. 12A and 128. This embodiment is different from the formerembodiment in that gate electrodes 5 are arranged in parallel with eachother and at right angles with respect to the common gate electrode 6,that the area underlying the cathode electrode 7 constitutes the mainregion and that the auxiliary region of the layer N, is closely adjacentto the common gate electrode 6.

FIG. l5 shows a modification of the thyristor shown in FIGS. l2A and12B. In this embodiment, the height of the cathode electrodes 7 in themain region to the left of dot and dash line 11 which divides the firstlayer is made higher than the height of the gate electrodes 5 and atemperature-compensating plate 7b is slidably urged against or solderedto the cathode electrode 7, thus forming airgaps 8a above gateelectrodes 5. With this construction, the thickness of the layer Ndivided by border line 1 1 into the main and auxiliary regions isuniform, so that this embodiment operates in the same manner as thatshown in F lGS. 12A and 128.

Thus, it will be clear that this invention provides a power transistorand controlled rectifier element wherein portions of the second layerare protruded through the first layer to be exposed at the surfacethereof, second electrodes are formed on these exposed portions and theexposed portions and the second electrodes contained therein areinsulatingly covered by a third electrode. For this reason, it ispossible to neatly arrange the second and third electrodes in spite ofintricated configurations, thus eliminating problems encountered in theprior grid-controlled semiconductor devices.

What is claimed is: 1. A semiconductor device comprising a substrateincluding at least first, second and third semiconductor layers havingalternately different conductivity types and laminated one upon theother, a third electrode connected to said first layer, a secondelectrode connected to said second layer and a means including a firstelectrode connected tothe last of said layers, said first layerincluding at least one main region, portions of said second layerprotruding through said first layer to be exposed at the surfacethereof, said second electrode being in ohmic contact with said exposedportions of said second layer, said third electrode overlying saidexposed portions of said second layer and said second electrode mountedon said portions and insulated from said exposed portions and saidsecond electrode, and said third electrode being in ohmic contact withsaid first layer in said main region.

2. A semiconductor device according to claim 1 wherein said first layerincludes an auxiliary region separated from said main region, saidsecond electrode in said main region is electrically connected with saidauxiliary region, and a fourth elec trode is connected to the exposedportion of said second layer at a position separated from said mainregion by said auxiliary region.

3. A semiconductor device according to claim 1 wherein said first layerincludes an auxiliary region contiguous with said main region, saidsecond electrode in said main region is electrically connected to saidauxiliary region and a fourth electrode is connected to the exposedportion of said second layer at a position separated from said mainregion by said auxiliary region.

4. A semiconductor device according to claim I wherein said exposedportions of said second layer in said main region are in the form ofparallel stripes and said third electrode covers all of said stripes.

5. A semiconductor device according to claim I wherein the first, secondand the third semiconductor layers of alternately different conductivitytypes are laminated one upon the other, said first electrode comprises acollector electrode, said second electrode a base electrode and saidthird electrode an emitter electrode whereby constituting a transistor.

6. A semiconductor device according to claim I wherein first to fourthsemiconductor layers having alternately different conductivity types arelaminated one upon the other, said first electrode comprises an anodeelectrode, said second electrode a gate electrode, and said thirdelectrode a cathode electrode whereby constituting asemiconductor-controlled rectifier element of the four layerconstruction.

7. A semiconductor device according to claim 3 wherein the thickness ofsaid first layer near the boundary between said main region and saidauxiliary region is made thinner than the remaining portions of saidfirst layer.

8. A semiconductor device according to claim 1 wherein said meansincluding said first electrode includes a semiconductor layer interposedbetween said first electrode and the last of said first, second andthird layers.

2. A semiconductor device according to claim 1 wherein said first layerincludes an auxiliary region separated from said main region, saidsecond electrode in said main region is electrically connected with saidauxiliary region, and a fourth electrode is connected to the exposedportion of said second layer at a position separated from said mainregion by said auxiliary region.
 3. A semiconductor device according toclaim 1 wherein said first layer includes an auxiliary region contiguouswith said main region, said second electrode in said main region iselectrically connected to said auxiliary region and a fourth electrodeis connected to the exposed portion of said second layer at a positionseparated from said main region by said auxiliary region.
 4. Asemiconductor device according to claim 1 wherein said exposed portionsof said second layer in said main region are in the form of parallelstripes and said third electrode covers all of said stripes.
 5. Asemiconductor device according to claim 1 wherein the first, second andthe third semiconductor layers of alternately different conductivitytypes are laminated one upon the other, said first electrode comprises acollector electrode, said second electrode a base electrode and saidthird electrode an emitter electrode whereby constituting a transistor.6. A semiconductor device according to claim 1 wherein first to fourthsemiconductor layers having alternately different conductivity types arelaminated one upon the other, said first electrode comprises an anodeelectrode, said second electrode a gate electrode, and said thirdelectrode a cathode electrode whereby constituting asemiconductor-controlled rectifier element of the four layerconstruction.
 7. A semiconductor device according to claim 3 wherein thethickness of said first layer near the boundary between said main regionand said auxiliary region is made thinner than the remaining portions ofsaid first layer.
 8. A semiconductor device according to claim 1 whereinsaid means including said first electrode includes a semiconductor layerinterposed between said first electrode and the last of said first,second and third layers.